Optimal systolic arrays for decimation filters
نویسندگان
چکیده
Systolic array designs are presented for decimation lters with an in nite input signal. The rst design is based on an existing design for convolution and is shown to be time optimal with respect to our criteria. Two new designs are derived by reducing the number of processing cells to the theoretical minimum while retaining optimal timing. EDICS number SP 5.1.4.
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ورودعنوان ژورنال:
- IEEE Trans. Signal Processing
دوره 43 شماره
صفحات -
تاریخ انتشار 1995